S5L1462B Datasheet, PDF (34/43 Pages) Samsung semiconductor – CD and DVD playback

S5L1462B
DPD TRACKING ERROR AMP
RF SIGNAL PROCESSOR
PLLCTL
ADVD
BDVD
CDVD
DDVD
SPEED_SEL
GAIN_TE1
+
TE1 ^GCA
EQ
+
Front
Mux
+
GCA
EQ
+
DPD_MUTE
PD_LIMIT
TBAL
comp
comp
VCPS
Phase
Detecter
LPF
DPDTE
to MUX5
Abnormal
Waveform
Detection Circuit
TE1OFST
FLT_CTL
HOLD_CTL
DPD TE BLOCK
TE1RES
DPDEQ1
INTERO
PDMIMITRES
FAULTO
DPDEQ2
GND
• The (A-D)DVD signal's gain is adjusted in the DPD input GAIN adjustment block by the gain selected by
Address 07H's GAIN_TE1 register. The signal is then compensated in the DPD EQUALIZER and input into the
COMPARATOR.
• The signal by passing through the COMPARATOR circuit is then adjusted for tracking balance by the VCPS
(Voltage Controlled Phase Shift) circuit, whose Delay Time is adjusted by Address 01H's register TBAL.
• The signal, after passing through the VCPS circuit, detects the phase difference between two signals through the
phase detector. The maximum width of the phase detector's output is limited by the output width limit set by
Add 07H's PD_LIMIT register.
• The abnormal waveform detection circuit compensates for a small or unstable input signal. It executes mute
when an abnormal waveform is detected, and turns the detection/compensation On or Off. The following are
qualified as abnormal waveforms:
 When the A+C COMPARATOR output is maintained for longer than 16T.
 When the - B+D COMPARATOR output is maintained for longer than 16T
 When the output of the abnormal waveform detection circuit goes "H".
 When the output of the abnormal waveform detection circuit goes 'H', then goes back to "L" at the next
RISING or FALLING EDGE.
• The output of the phase detector is output through the low pass filter. It is input into the MUX5 then output to the
TE block.
• The DPD TE OFFSET is a function to correct the circuit OFFSET after phase comparison. It eliminates any
OFFSET existing within the LPF block.
• The DPD MUTE mutes the DPD TE while correcting the DPD Offset. Mute is carried out when Add 07H's
DPD_MUTE register is "H", the external DPDMUTE block's input voltage is "H", and the INTERRUPT output is
"H".
• When TE_SEL is not in DPD MODE, the DPD BLOCK's power is turned off.
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