M312L2920BT Datasheet, PDF (3/23 Pages) Samsung semiconductor – DDR SDRAM Registered Module

512MB, 1GB, 2GB TSOP Registered DIMM
DDR SDRAM
184Pin Registered DIMM based on 512Mb B-die (x4, x8)
Ordering Information
Part Number
M383L6523BTS-CAA/A2/B0/A0
M383L2923BTS-CAA/A2/B0/A0
M383L2920BTS-CAA/A2/B0/A0
M383L5628BT1-CAA/A2/B0/A0
M312L6523BTS-CAA/A2/B0/A0
M312L2923BTS-CAA/A2/B0/A0
M312L2920BTS-CAA/A2/B0/A0
M312L5628BT0-CAA/A2/B0/A0
Density
512MB
1GB
1GB
2GB
512MB
1GB
1GB
2GB
Organization
64M x 72
128M x 72
128M x 72
256M x 72
64M x 72
128M x 72
128M x 72
256M x 72
Component Composition
64Mx8( K4H510838B) * 9EA
64Mx8( K4H510838B) * 18EA
128Mx4( K4H510438B) * 18EA
st.256Mx4( K4H1G0638B) * 18EA
64Mx8( K4H510838B) * 9EA
64Mx8( K4H510838B) * 18EA
128Mx4( K4H510438B) * 18EA
st.256Mx4( K4H1G0638B) * 18EA
Heihgt
1,700mil
1,700mil
1,700mil
1,700mil
1,200mil
1,200mil
1,200mil
1,200mil
Operating Frequencies
Speed @CL2
Speed @CL2.5
CL-tRCD-tRP
AA(DDR266@CL=2)
133MHz
133MHz
2-2-2
A2(DDR266@CL=2)
133MHz
133MHz
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
2.5-3-3
A0(DDR200@CL=2)
100MHz
-
2-2-2
Feature
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• 1,700mil / 1,200mil height & double sided
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Revison 1.0 December, 2003