M312L2920BT Datasheet, PDF (12/23 Pages) Samsung semiconductor – DDR SDRAM Registered Module

512MB, 1GB, 2GB TSOP Registered DIMM
DDR SDRAM
AC Operating Conditions
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
VREF + 0.31
0.7
0.5*VDDQ-0.2
Max
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
Unit
V
V
V
V
Note
3
3
1
2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
Output
RT =50?
Z0=50?
CLOAD =30pF
VREF
=0.5*V DDQ
Input/Output Capacitance
Output Load Circuit (SSTL_2)
(VDD=2.5V, VDDQ=2.5V, TA= 25?C, f=1MHz)
Parameter
Symbol
M383(12)L6523BTS, M383(12)L2920BTS
Min
Max
Unit
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,W E ) CIN1
9
11
pF
Input capacitance(CKE0)
CIN2
9
11
pF
Input capacitance( CS0)
CIN3
9
11
pF
Input capacitance( CLK0, CLK0 )
CIN4
11
12
pF
Input capacitance(DM0~DM8)
CIN5
10
11
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
10
11
pF
Data input/output capacitance (CB0~CB7)
Cout2
10
11
pF
Parameter
Symbol
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0,CKE1)
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK0 )
Input capacitance(DM0~DM8)
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
M383(12)L2923BTS, M383(12)L5628BT1(0)
Min
Max
9
11
9
11
9
11
11
12
14
16
14
16
14
16
Unit
pF
pF
pF
pF
pF
pF
pF
Revison 1.0 December, 2003