K4T1G044QM Datasheet, PDF (3/29 Pages) Samsung semiconductor – 1Gb M-die DDR2 SDRAM Specification

1Gb M-die DDR2 SDRAM
0. Ordering Information
Organization
DDR2-533 4-4-4
256Mx4
K4T1G044QM-ZCD5
128Mx8
K4T1G084QM-ZCD5
64Mx16
K4T1G164QM-ZCD5
Note : Speed bin is in order of CL-tRCD-tRP
DDR2 SDRAM
DDR2-400 3-3-3
K4T1G044QM-ZCCC
K4T1G084QM-ZCCC
K4T1G164QM-ZCCC
Package
Lead-Free
Lead-Free
Lead-Free
1.Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-533
4-4-4
4
15
15
55
DDR2-400
3-3-3
3
15
15
55
Units
tCK
ns
ns
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f_CK for 400Mb/sec/pin, 267MHz f_CK for
533Mb/sec/pin.
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended
data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refresh Period 7.8us at lower than T_CASE
85°C, 3.9us at 85°C < T_CASE < 95 °C
• Package: 68ball FBGA - 256Mx4/128Mx8 , 92ball
FBGA - 64Mx16
• All of Lead-free products are compliant for RoHS
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os
x 8 banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8
banks device. This synchronous device achieves high
speed double-data-rate transfer rates of up to
533Mb/sec/pin (DDR2-533) for general applications.
The chip is designed to comply with the following key
DDR2 SDRAM features such as posted CAS with additive
latency, write latency = read latency - 1, Off-Chip
Driver(OCD) impedance adjustment and On Die Termina-
tion.
All of the control and address inputs are synchronized with
a pair of externally supplied differential clocks. Inputs are
latched at the crosspoint of differential clocks (CK rising
and CK falling). All I/Os are synchronized with a pair of
bidirectional strobes (DQS and DQS) in a source synchro-
nous fashion. The address bus is used to convey row, col-
umn, and bank address information in a RAS/CAS
multiplexing style. For example, 1Gb(x4) device receive
14/11/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V
power supply and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 68ball FBGAs(x4/x8)
and in 92ball FBGAs(x16).
Note: The functionality described and the timing specifica-
tions included in this data sheet are for the DLL Enabled
mode of operation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features
which are described in “DDR2 SDRAM Device Operation & Timing Diagram”.
Page 3 of 29
Rev.1.1 Jan. 2005