K4T1G044QM Datasheet, PDF (19/29 Pages) Samsung semiconductor – 1Gb M-die DDR2 SDRAM Specification

1Gb M-die DDR2 SDRAM
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
Symbol
DDR2-533
min max
DQ output access time tAC
from CK/CK
-500
+500
DQS output access
time from CK/CK
tDQSCK
-450
+450
CK high-level width
tCH
0.45
0.55
CK low-level width
tCL
0.45
0.55
CK half period
tHP
min(tCL
x
, tCH)
Clock cycle time, CL=x tCK
3750
8000
DQ and DM input hold tDH(base)
225
x
time
DQ and DM input
tDS(base)
100
x
setup time
Control & Address
input pulse width for
each input
tIPW
0.6
x
DQ and DM input
pulse width for each
input
tDIPW
0.35
x
Data-out high-
tHZ
impedance time from
CK/CK
x
tAC
max
DQS low-impedance
time from CK/CK
tLZ(DQS)
tAC
tAC
min
max
DQ low-impedance
time from CK/CK
tLZ(DQ)
2* tAC
tAC
min
max
DQS-DQ skew for
DQS and associated
DQ signals
tDQSQ
x
300
DQ hold skew factor
tQHS
x
400
DQ/DQS output hold
tQH
time from DQS
tHP -
x
tQHS
Write command to first tDQSS
DQS latching transition
-0.25
0.25
DQS input high pulse tDQSH
0.35
x
width
DQS input low pulse
width
tDQSL
0.35
x
DQS falling edge to
CK setup time
tDSS
0.2
x
DQS falling edge hold
time from CK
tDSH
0.2
x
DDR2-400
min
max
-600
+600
-500
+500
0.45
0.45
min(tCL
, tCH)
5000
275
0.55
0.55
x
8000
x
150
x
0.6
x
0.35
x
x
tAC
max
tAC
tAC
min
max
2* tAC
tAC
min
max
x
350
x
450
tHP -
x
tQHS
-0.25
0.25
0.35
x
0.35
x
0.2
x
0.2
x
Units Notes
ps
ps
tCK
tCK
ps
20,21
ps
24
ps
15,16,
17,20
ps
15,16,
17,21
tCK
tCK
ps
ps
27
ps
27
ps
22
ps
21
ps
tCK
tCK
tCK
tCK
tCK
Page 19 of 29
DDR2 SDRAM
Rev.1.1 Jan. 2005