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K4D553235F-GC Datasheet, PDF (3/18 Pages) Samsung semiconductor – 256M GDDR SDRAM | |||
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K4D553235F-GC
256M GDDR SDRAM
2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
⢠1.8V ± 0.1V power supply for device operation
⢠1.8V ± 0.1V power supply for I/O interface
⢠SSTL_18 compatible inputs/outputs
⢠4 banks operation
⢠MRS cycle with address key programs
-. Read latency 4, 5 and 6 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
⢠All inputs except data & DM are sampled at the positive
going edge of the system clock
⢠Differential clock input
⢠No Wrtie-Interrupted by Read Function
⢠4 DQSâs ( 1DQS / Byte )
⢠Data I/O transactions on both edges of Data strobe
⢠DLL aligns DQ and DQS transitions with Clock transition
⢠Edge aligned data & data strobe output
⢠Center aligned data & data strobe input
⢠DM for write masking only
⢠Auto & Self refresh
⢠32ms refresh period (4K cycle)
⢠144-Ball FBGA
⢠Maximum clock frequency up to 450MHz
⢠Maximum data rate up to 900Mbps/pin
ORDERING INFORMATION
Part NO.
K4D553235F-GC25
K4D553235F-GC2A
K4D553235F-GC33
Max Freq.
400MHz
350MHz
300MHz
* K4D553235F-VC is the Lead Free package part number.
Max Data Rate
800Mbps/pin
700Mbps/pin
600Mbps/pin
Interface
SSTL_18
Package
144-Ball FBGA
GENERAL DESCRIPTION
FOR 2M x 32Bit x 4 Bank DDR SDRAM
The K4D553235F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
32 bits, fabricated with SAMSUNGâs high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 3.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
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Rev 1.6 (May 2005)
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