K4D553235F-GC Datasheet, PDF (15/18 Pages) Samsung semiconductor – 256M GDDR SDRAM

K4D553235F-GC
256M GDDR SDRAM
AC CHARACTERISTICS (II)
Parameter
Symbol
Row cycle time
tRC
Refresh row cycle time
tRFC
Row active time
tRAS
RAS to CAS delay for Read
tRCDRD
RAS to CAS delay for Write
tRCDWR
Row precharge time
tRP
Last data in to Row precharge @Normal
Precharge
tWR
Last data in to Row precharge @Auto Pre-
charge
tWR_A
Auto precharge write recovery + Precharge tDAL
Row active to Row active
tRRD
Last data in to Read command
tCDLR
Col. address to Col. address
tCCD
Mode register set cycle time
tMRD
Exit self refresh to read command
tXSR
Power down exit time
tPDEX
Refresh interval time
tREF
-25
Min
Max
45
-
50
-
28.6
100K
15
-
10
-
15
-
15
-
6
-
30
-
4
-
2
-
1
-
4
-
200
-
3tCK+
tIS
-
7.8
-
-2A
Min
Max
45.8
-
51.5
-
28.6
100K
16.5
-
11.4
-
16.5
-
16.5
-
6
-
33
-
4
-
2
-
1
-
3
-
200
-
3tCK+
tIS
-
7.8
-
-33
Min
49.5
56.1
33
16.5
11.4
16.5
Max
-
-
100K
-
-
-
16.5
-
5
-
33
-
3
-
2
-
1
-
3
-
200
-
3tCK+
tIS
-
7.8
-
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
2. The number of clock of tRC is restricted by the number of clock of tRAS and tRP
3. The number of clock of tWR_A is fixed. It can’t be changed by tCK. tWR_A is related with CL. It is equal to CL+1tCK.
4. tRCDWR is equal to tRCDRD-2tCK and the number of clock can not be lower than 2tCK.
5. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer unconditionally.
Unit Note
ns 2,5
ns
5
ns
5
ns
5
ns 4,5
ns
5
ns 1,5
tCK 1,3
ns 3,5
tCK
tCK 1
tCK
tCK
tCK
ns
us
- 15 -
Rev 1.6 (May 2005)