DS_K7N163601A Datasheet, PDF (3/24 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 Pipelined NtRAM

K7N163601A
K7N161801A
512Kx36 & 1Mx18 Pipelined NtRAM^TM
512Kx36 & 1Mx18-Bit Pipelined NtRAM^TM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no da ta-
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• 100-TQFP-1420A
• 165FBGA(11x15 ball aray) with body size of 13mmx15mm.
• Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
PARAMETER
Symbol -25 -20 -16 -13 Unit
Cycle Time
tCYC 4.0 5.0 6.0 7.5 ns
Clock Access Time
tCD 2.6 3.2 3.5 4.2 ns
Output Enable Access Time tOE 2.6 3.2 3.5 4.2 ns
GENERAL DESCRIPTION
The K7N163601A and K7N161801A are 18,874,368-bits Syn-
chronous Static SRAMs.
The N tRAM ^TM, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N163601A and K7N161801A are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP and 165FBGA packages. Multiple power
and ground pins minimize ground bounce.
LOGIC BLOCK DIAGRAM
A [0:18]or
A [0:19]
LBO
A 0~A 1
ADDRESS
REGISTER ^{A2~A 18 or A 2~A 19}
BURST
ADDRESS
COUNTER
A′0~A ′1
512Kx36, 1Mx18
MEMORY
ARRAY
CLK
K
CKE
CS1
CS2
CS2
ADV
WE
B Wx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7 or D Q a0 ~ DQb8
DQPa ~ DQPd
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
DATA-IN
K REGISTER
DATA-IN
K REGISTER
CONTROL
LOGIC
36 or 18
K OUTPUT
REGISTER
BUFFER
NtRAM ^TM and No Turnaround Random Access Memory are trademarks of Samsung.
-3-
Nov. 2003
Rev 3.0