DS_K7N163601A Datasheet, PDF (17/24 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 Pipelined NtRAM

K7N163601A
K7N161801A
512Kx36 & 1Mx18 Pipelined NtRAM^TM
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Input High Level ( 3.3V I/O / 2.5V I/O )
Input Low Level ( 3.3V I/O / 2.5V I/O )
Output High Voltage( 3.3V I/O / 2.5V I/O )
Output Low Voltage( 3.3V I/O / 2.5V I/O )
Symbol
Min
Typ
Max
Unit
VDD
3.135
3.3
3.465
V
VI H
2.0 / 1.7
-
V DD+0.3
V
VIL
-0.3
-
0.8 / 0.7
V
VO H
2.4 / 2.0
-
-
V
VOL
-
-
0.4 / 0.4
V
NOTE : The input level of SRAM pin is to follow the SRAM DC specification.
1. In Case of I/O Pins, the Max. VIH=VDDQ +0.3V.
JTAG AC TEST CONDITIONS
Parameter
Input High/Low Level( 3.3V I/O , 2.5V I/O )
Input Rise/Fall Time( 3.3V I/O , 2.5V I/O )
Input and Output Timing Reference Level
Symbol
VIH/VIL
TR/TF
Min
3.0/0 , 2.5/0
1.0/1.0 , 1.0/1.0
V DDQ/2
Unit
V
ns
V
Note
1
Note
JTAG AC Characteristics
Parameter
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
JTAG TIMING DIAGRAM
TCK
tCHCH
TMS
TDI
PI
(SRAM)
tCLQV
TDO
Symbol
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
Min
50
20
20
5
5
5
5
5
5
0
tMVCH
tDVCH
tCHMX
tCHCL
tCHDX
tSVCH
tCHSX
- 17 -
Max
-
-
-
-
-
-
-
-
-
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLCH
Note
Nov. 2003
Rev 3.0