DS_K7N163601A Datasheet, PDF (13/24 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 Pipelined NtRAM

K7N163601A
K7N161801A
512Kx36 & 1Mx18 Pipelined NtRAM^TM
Dout
Output Load(A)
Zo=50Ω
RL=50Ω
30pF*
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319Ω / 1667Ω
353Ω / 1538Ω
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0 to 70°C)
PARAMETER
SYMBOL
-25
MIN MAX
-20
MIN MAX
-16
MIN MAX
-13
MIN MAX
UNIT
Cycle Time
tCYC
4.0
-
5.0
-
6.0
-
7.5
-
ns
Clock Access Time
Output Enable to Data Valid
tCD
-
2.6
-
3.2
-
3.5
-
4.2
ns
tOE
-
2.6
-
3.2
-
3.5
-
4.2
ns
Clock High to Output Low-Z
tLZC
1.5
-
1.5
-
1.5
-
1.5
-
ns
Output Hold from Clock High
Output Enable Low to Output Low-Z
tOH
1.5
-
1.5
-
1.5
-
1.5
-
ns
tLZOE
0
-
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
tHZOE
-
2.6
-
3.0
-
3.0
-
3.5
ns
Clock High to Output High-Z
tHZC
-
2.6
-
3.0
-
3.0
-
3.5
ns
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
tCH
1.7
-
2.0
-
2.2
-
3.0
-
ns
tCL
1.7
-
2.0
-
2.2
-
3.0
-
ns
tAS
1.2
-
1.4
-
1.5
-
1.5
-
ns
CKE Setup to Clock High
tCES
1.2
-
1.4
-
1.5
-
1.5
-
ns
Data Setup to Clock High
tDS
1.2
-
1.4
-
1.5
-
1.5
-
ns
Write Setup to Clock High (WE, BWX)
tWS
1.2
-
1.4
-
1.5
-
1.5
-
ns
Address Advance Setup to Clock High
tADVS
1.2
-
1.4
-
1.5
-
1.5
-
ns
Chip Select Setup to Clock High
tCSS
1.2
-
1.4
-
1.5
-
1.5
-
ns
Address Hold from Clock High
CKE Hold from Clock High
Data Hold from Clock High
tAH
0.3
-
0.4
-
0.5
-
0.5
-
ns
tCEH
0.3
-
0.4
-
0.5
-
0.5
-
ns
tDH
0.3
-
0.4
-
0.5
-
0.5
-
ns
Write Hold from Clock High (WE , BW X)
tWH
0.3
-
0.4
-
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
tADVH
0.3
-
0.4
-
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
ZZ High to Power Down
tCSH
0.3
-
0.4
-
0.5
-
0.5
-
ns
tPDS
2
-
2
-
2
-
2
-
cycle
ZZ Low to Power Up
tPUS
2
-
2
-
2
-
2
-
cycle
Note s : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
5. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tH Z C, which is a Max. parameter(worst case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
- 13 -
Nov. 2003
Rev 3.0