K4R571669D Datasheet, PDF (16/20 Pages) Samsung semiconductor – 256/288Mbit RDRAM(D-die)

K4R571669D/K4R881869D
Direct RDRAM^™
Timing Characteristics
Table 12: Timing Characteristics
Symbol
t_Q
t_QR, t_QF
t_Q1
t_HR
t_QR1, t_QF1
t_PROP1
t_NAPXA
t_NAPXB
t_PDNXA
t_PDNXB
t_AS
t_SA
t_ASN
t_ASP
Parameter
CTM-to-DQA/DQB output time @ t_CYCLE=1.875ns
CTM-to-DQA/DQB output time @ t_CYCLE=2.5ns
DQA/DQB output rise and fall times @ t_CYCLE=1.875ns
DQA/DQB output rise and fall times @ t_CYCLE=2.5ns
SCK(neg)-to-SIO0 delay @ C_LOAD,MAX = 20pF (SD read data valid).
SCK(pos)-to-SIO0 delay @ C_LOAD,MAX = 20pF (SD read data hold).
SIO_OUT rise/fall @ C_LOAD,MAX = 20pF
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C_LOAD,MAX = 20pF
NAP exit delay - phase A
NAP exit delay - phase B
PDN exit delay - phase A
PDN exit delay - phase B
ATTN-to-STBY power state delay
STBY-to-ATTN power state delay
ATTN/STBY-to-NAP power state delay
ATTN/STBY-to-PDN power state delay
Min
-0.195^a
-0.260^a,b
0.2
0.2
-
2
-
-
-
-
-
-
-
-
-
-
Max
+0.195^a
+0.260^a,b
0.32
0.45
10
-
12
20
50
40
4
9000
1
0
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
Figure(s)
Figure 58
Figure 58
Figure 61
Figure 61
Figure 61
Figure 61
Figure 50
Figure 50
Figure 50
Figure 50
Figure 48
Figure 48
Figure 49
Figure 49
a. t_Q,MIN and t_Q,MAX for other t_CYCLE values can be interpolated between or extrapolated from the timings at the 3 specified t_CYCLE values.
b.This parameter also applies to a-1066 part when operated with t_CYCLE = 2.50ns
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Version 1.4 July 2002