K4R571669D Datasheet, PDF (15/20 Pages) Samsung semiconductor – 256/288Mbit RDRAM(D-die)

K4R571669D/K4R881869D
Direct RDRAM^™
Symbol
t_CD
t_FRM
t_NLIMIT
t_REF
t_BURST
t_CCTRL
t_TEMP
t_TCEN
t_TCAL
t_TCQUIET
t_PAUSE
Table 11: Timing Conditions
Parameter
CTM/CFM stable after NAP/PDN entry
ROW packet to COL packet ATTN framing delay
Maximum time in NAP mode
Refresh interval
Interval after PDN or NAP (with self-refresh) exit in which all
banks of the RDRAM device must be refreshed at least once.
Current control interval
Temperature control interval
TCE command to TCAL command
TCAL command to quiet window
Quiet window (no read data)
RDRAM device delay (no RSL operations allowed)
Min
100
7
34 t_CYCLE
150
2
140
Max
-
-
10.0
32
200
100ms
100
-
2
-
200.0
Unit
t_CYCLE
t_CYCLE
µs
ms
Figure(s)
Figure 49
Figure 48
Figure 47
Figure 52
µs
Figure 53
ms/t_CYCLE
ms
t_CYCLE
t_CYCLE
t_CYCLE
µs
Figure 54
Figure 55
Figure 55
Figure 55
Figure 55
page 38
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. t_S,MIN and t_H,MIN for other t_CYCLE values can be interpolated between or extrapolated from the timings at the 2 specified t _CYCLE values.
c. This parameter also applies to a-1066 part when operated with t_CYCLE = 2.50ns
d. With V_IL,CMOS=0.5V_CMOS-0.4V and V_IH,CMOS=0.5V_CMOS+0.4V
e. Effective hold becomes t_H4’=t_H4+[PDNXA•64•t_SCYCLE+t_PDNXB,MAX]-[PDNX•256•t_SCYCLE]
if [PDNX•256•t_SCYCLE] < [PDNXA•64•t_SCYCLE+t_PDNXB,MAX]. See Figure 50.
Page 13
Version 1.4 July 2002