K4D551638F-TC Datasheet, PDF (15/16 Pages) Samsung semiconductor – 256Mbit GDDR SDRAM

K4D551638F-TC
Target Spec
256M GDDR SDRAM
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at
least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read
command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data
to read command (tCDLR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins
before the read command is initiated will actually be written to the memory. Read command interrupting write can not be
issued at the next clock edge of that of write command.
< Burst Length=8, CAS Latency=3 >
0
1
2
3
CK
CK
4
5
6
Command NOP
WRITE
NOP
tDQSSmax
NOP
NOP
tCDLR
READ
NOP
CAS Latency=3
DQS
t_WPRES*5
DQ ′s
tDQSSmin
Din 0
Din 1
Din 2
Din 3 Din 4
tCDLR
Din 5
Din 6
Din 7
CAS Latency=3
DQS
DQ ′s
t_WPRES*5
Din 0
Din 1
Din 2
Din 3
Din 4
Din 5
Din 6
Din 7
DM
7
NOP
8
NOP
Dout 0 Dout 1
Dout 0 Dout 1
The following function established how a Read command may interrupt a Write burst and which input data is not written
into the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The
case where the Write to Read delay is 1 clock cycle is disallowed
2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich imme-
diately precede the interrupting Read operation and the input data word which immediately follows the interrupting
Read operation
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the
memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them during a read oper-
ation.
4. If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM.
* This function is only supported in 200/166MHz.
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Rev 1.7 (June 2004)