K4D551638F-TC Datasheet, PDF (13/16 Pages) Samsung semiconductor – 256Mbit GDDR SDRAM

K4D551638F-TC
Target Spec
256M GDDR SDRAM
AC CHARACTERISTICS
Parameter
Symbol
-33
Min Max
CK cycle time
CL=3 tCK
3.3
10
CK high level width
tCH
0.45 0.55
CK low level width
tCL
0.45 0.55
DQS out access time from CK tDQSCK -0.6 0.6
Output access time from CK
tAC
-0.6 0.6
Data strobe edge to Dout edge tDQSQ
-
0.35
Read preamble
tRPRE
0.9
1.1
Read postamble
tRPST
0.4
0.6
CK to valid DQS-in
tDQSS
0.85 1.15
DQS-In setup time
tWPRES 0
-
DQS-in hold time
tWPREH 0.35
-
DQS write postamble
tWPST
0.4
0.6
DQS-In high level width
tDQSH
0.4
0.6
DQS-In low level width
tDQSL
0.4
0.6
Address and Control input setup tIS
0.9
-
Address and Control input hold tIH
0.9
-
DQ and DM setup time to DQS tDS
0.35
-
DQ and DM hold time to DQS tDH
0.35
-
tCLmin
Clock half period
tHP
or
-
tCHmin
Data output hold time from DQS tQH
tHP-
0.35
-
-36
Min Max
3.6
10
0.45 0.55
0.45 0.55
-0.6 0.6
-0.6 0.6
-
0.4
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.4
-
0.4
-
tCLmin
or
-
tCHmin
tHP-0.4 -
-40
Min Max
4.0
10
0.45 0.55
0.45 0.55
-0.6 0.6
-0.6 0.6
-
0.4
0.9
1.1
0.4
0.6
0.85 1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.4
-
0.4
-
tCLmin
or
-
tCHmin
tHP-0.4 -
-50
Min Max
5.0
10
0.45 0.55
0.45 0.55
-0.55 0.55
-0.65 0.65
-
0.4
0.9
1.1
0.4
0.6
0.72 1.28
0
-
0.25
-
0.4
0.6
0.35
-
0.35
-
0.6
-
0.6
-
0.4
-
0.4
-
tCLmin
or
-
tCHmin
tHP-0.5 -
-60
Min Max
6.0
12
0.45 0.55
0.45 0.55
-0.6 0.6
-0.7 0.7
-
0.45
0.9
1.1
0.4
0.6
0.75 1.25
0
-
0.25
-
0.4
0.6
0.35
-
0.35
-
0.8
-
0.8
-
0.45
-
0.45
-
tCLmin
or
-
tCHmin
tHP-
0.55
-
Unit Note
ns
tCK
tCK
ns
ns
ns
1
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
1
ns
1
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming
the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
- 13 -
Rev 1.7 (June 2004)