BU9829GUL-W_10 Datasheet, PDF (9/17 Pages) Rohm – WL-CSP EEPROM family SPI BUS

BU9829GUL-W
Technical Note
6. WRSR (WRITE STATUS RESISTER)
This “Write Status Register” command writes the data, two (BP1, BP0) of the eight bits, into the status register. Write
protection is set by BP1 and BP0 bits. After CSB goes low, Op.code of “Read Status Register” need to sent. Between the
rising edge of the 15th clock and it or the 16th clock, the rising edge of CSB initiates high voltage cycle, which writes the
data into non-volatile memory array, but the command is cancelled if CSB is high except that period. It takes maximum
5ms in high voltage cycle (tE/W) as well as “Write”.Block write protection is determined by BP1 and BP0 bits, which is
selected from quarter, half and the entire memory array. (See Table2 BLOCK WRITE PROTECTION>)
CSB
SCK
SI
0
1
2
3
4
5
6
78
9 10 11 12 13 14 15
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00 0 0 0
10
1*
*
*
* BP1 BP0 *
*
SO ^Hi-Z
* Don’t care
Fig. 38 WRITE STATUS REGISTER WRITE CYCLE TIMING
7. VSET READ
The VSET data stored in the memory are clocked out after “VSET Read” instruction set address 800h is received.
After CSB goes low, the address (800h) need to be sent following by Op.code of “Read”. 0 are clocked out from D7 to D2
and the VSET data are clocked out from D1 to D0, which is start at the falling edge of 23th clock.
CSB
SCK
0 1 2 3 4 5 6 78
12 13
23 24
30
SI
00 0 0 00
11 * * 1 0
00
SO ^Hi-Z
0
0
0
0
VSET VSET
1
0
Fig.39 VSET READ CYCLE TIMIING
* Don’t care
8. VSET WRITE
This “Write” command set address 800h writes VSET data into VSET1 and VSET0 memory array. After CSB goes low,
the address (800h) and VSET data need to be sent following by Op.code of “VSET Write”. Between the rising edge of the
29th clock and it of the 30th clock, the rising edge of CSB initates high voltage cycle, which writes the data into
non-volatile memory array, but the command is cancelled if CSB is high except that period. It takes maximum 5ms in high
voltage cycle (tE/W). The device does not receive any command except for “Read Status Register” command during this
high voltage cycle.
CSB
SCK
0 1 _{2 3 4 5 6 78}
12 13
23 24
30 31
SI
00 0 0 00
SO ^Hi-Z
10*
*
10 0 0 0 *
*
*
*
VSET VSET
1
0
* Don’t care
Fig. 40 VSET WRITE CYCLE TIMING
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9/16
2010.09 - Rev.A