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BU9829GUL-W_10 Datasheet, PDF (7/17 Pages) Rohm – WL-CSP EEPROM family SPI BUS | |||
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BU9829GUL-W
Technical Note
âFunctional description
âStatus Register
The device has status register.
Status register consists of 8bits and is shown following parameters.
2 bits (BP0 and BP1) are set by âWrite Status Registerâ commands, which are non-volatile.
Specification of endurance and data retention are as well as memory array. WEN bit is set by âWrite Enableâ and âWrite
Disableâ commands. After power become on, the device is disable mode. R / B bit is a read-only and status bit.
The device is clocked out value of the status register by âRead Status Registerâ command input.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
BP1
BP0
WEN
R /B
Bit
BP0/BP1
WEN
R /B
Definition
Block write protection for memory array
(EEPROM)
Write enable/disable status bit
WEN=0 : write disable
WEN=1 : write enable
READY/BUSY status bit
R / B =0 : READY
R / B =1 : BUSY
BP1 BP0 Block Write Protection
0
0
0
1
1
0
1
1
NONE
600h-7FFh
400h-7FFh
000h-7FFh
âInstruction code
Instruction
WREN
WRDI
READ
WRITE
RDSR
WRSR
VSET_READ
VSET_WRITE
âTiming chart
1. WRITE ENABLE
CSB
Operation
Write enable
Write disable
Read data from memory array
Write data to memory array
Read status register
Write status registeï½
Read VSET data
Write VSET data
Op.Code
0000 0110
0000 0100
0000 0011
0000 0010
0000 0101
0000 0001
0000 0011
0000 0010
2. WRITE DISABLE
CSB
Address
-
-
A10 ï½ A0
A10 ï½ A0
-
-
800h
800h
SCK
0
1
2
3
4
5
6
7
SCK
0
1
2
3
4
5
6
7
SI
0
0
0
0
0
1
1
0
SI
0
0
0
0
0
1
00
SO
Hi-Z
SO
Hi-Z
Fig.33 WRITE ENABLE CYCLE TIMING
Fig.34 WRITE DISABLE CYCLE TIMING
âThe device has both of the enable and disable mode. After âWrite Enableâ is executed, the device becomes in the enable
mode. After âWrite Disableâ is executed, the device becomes in the disable mode. After CSB goes low, each of Op.code
is recognized at the rising edge of 7th clock. Each of instructions is effective inputting seven or more SCK clocks. This
âWrite Enableâ instruction must be proceeded before the any write commands. The device ignores inputting the any write
commands in the disable mode. Once the any write commands is executed in the enable mode, the device becomes the
disable mode. After the power become on, the device is in the disable mode.
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© 2010 ROHM Co., Ltd. All rights reserved.
7/16
2010.09 - Rev.A
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