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BU9829GUL-W_10 Datasheet, PDF (10/17 Pages) Rohm – WL-CSP EEPROM family SPI BUS | |||
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BU9829GUL-W
Technical Note
âEEPROM soft ware
âREAD, VSET_READ, RDSR Command cancel
Cancel of these commands is possible by changing CSB pin to âHIGHâ in all sections.
OPECODE
ADDRESS
DATA
OPECODE
DATA
8bit
8bit
8bit
Cancel is possible
Fig.41 READ, VSET_READ Cancel Timing
8bit
8bit
Cancel is possible
Fig.42 RDSR Cancel Timing
âWRITE, PAGE_WRITE, VSET_WRITEãWRSR Command cancel
Cancel of these write command is possible by changing CSB pin to âHIGHâ in opecode, address and data input sections
(section a~b), but it is impossible after data input section (section c~d), if Vcc1 is OFF during tE/W, please write again
because write data is not guaranteed in specified address, if SCK and CSB rise at the same time in section C, command
is instability. It is recommend to rise CSB in âSCK=Lâ section.
OPECODE ADDRESS
DATA(n)
tE/W
SCK
8bit
8bit
a
8bit
b
d
c
SI
AN ENLARGEMENT
D7 D6 D5 D4 D3 D2 D1 D0
b
c
Fig.43 WRITE, PAGE_WRITE, VSET_WRITE READ VSET_READ Cancel Timing
OPECODE
8bit
a
DATA(n)
8bit
b
c
tE/W
8bit
d
SCK
14 15 16 17
AN ENLARGEMENT SI
D1 D0
b
c
d
Fig.44 WRSR Cancel Timing
âWREN, WRDI command cancel
Cancel of these commands is possible by changing CSB pin to âHIGHâ of opecode to rising 8 clk, but it is impossible after
rising 8 clk. In the case, please send WREN or WRDI cancel timing command again.
OPECODE
8bit
a
7
8
9
AN ENLARGEMENT
b
a
b
Fig.45 WREN, WRDI Cancel Timing
âData polling
If RDSR command is carried out daring tE/W, according to out put data ( R / B bit), to monitor READY/BUSY state is
possible. Because of this, it is possible to send next command earlier than regular programming time (tE/W MAX=5ms).
If R / B bit is â1â, EEPROMâs state is âBUSYâ. If this becomes â0â, it is possible to send next command to change
EEPROM to âREADYâ state. Status register data read by this command in tE/W is not data written by WRSR command but
old data before. Status register data in each section is shown below.
CSB
SCK
SI
SO
READ STATUS
REGISTOR
a=0Ch
During WRSR Commandï¼tE/Wï¼
BUSY
READY
WRITE STATUS
REGISTOR
b=(00h)
READ STATUS
REGISTOR
c=0Fh
READ STATUS
REGISTOR
d=0Ch
READ STATUS
REGISTOR
e=00h
Fig.46 Status register data in each section
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© 2010 ROHM Co., Ltd. All rights reserved.
10/16
2010.09 - Rev.A
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