BU6566GVW_09 Datasheet, PDF (9/17 Pages) Rohm – Camera Image Processors Compatible with JPEG Image

BU6566GVW, BU6568GV
Technical Note
●Timing Chart
1. HOST interface timing
1.1 System timing
Table 1.1-1 BU6566GVW timing conditions (system)
Symbol
Details
MIN.
TYP.
MAX.
tXIN
Clock input cycle
33.0
-
-
DutyXIN
Clock duty
45.0
50.0
55.0
tSCLK
System clock cycle
33.0
-
-
DutySCLK
System clock duty
33.3
50.0
66.7
tCAMCKO
Camera clock output cycle
33.0
-
-
DutyCAMCKO Camera clock output duty
33.3
50.0
66.7
tCAMCKI
Camera clock input cycle
66.0
-
-
DutyCAMCKI Camera clock input duty
40.0
50.0
60.0
tRESETB
RESETB "L" pulse width
＊Regulation all at threshold of VDDIO×1/2
1.0
-
-
Table 1.1-2 BU6568GV timing conditions (system)
Symbol
Details
MIN.
TYP.
MAX.
tXIN
Clock input cycle
33.0
-
-
DutyXIN
Clock duty
45.0
50.0
55.0
tSCLK
System clock cycle
19.2
-
-
DutySCLK
System clock duty
33.3
50.0
66.7
tCAMCKO
Camera clock output cycle
19.2
-
-
DutyCAMCKO Camera clock output duty
45.0
50.0
55.0
tCAMCKI
Camera clock input cycle
19.2
-
-
DutyCAMCKI Camera clock input duty
45.0
50.0
55.0
tRESETB
RESETB "L" pulse width
＊Regulation all at threshold of VDDIO×1/2
1.0
-
-
1.2 Register (including RAM via register) write timing.
tWC
tAS
A2,A1
CSB（WRB）
WRB（CSB）
RDB
D[15:0]
Address Input
tCS
tWW
tDS
Write
tAH
tCH
tDH
Data
tWAIT
Unit
Conditions
ns
% "H" width / cycle
ns
% "H" width / cycle
ns
% “"H" width / cycle
ns
% "H" width / cycle
us
Unit Conditions
ns
% "H" width / cycle
ns
% "H" width / cycle
ns
% "H" width / cycle
ns
% "H" width / cycle
us
Table 1.2-1 BU6566GVW timing conditions（RAM, register write cycle）
Symbol
Details
MIN. TYP. MAX. Unit
tWC
Write cycle time
70
-
-
ns
tAS
Address setup time before WRB(CSB) falling
-5
-
-
ns
tAH
Address hold time after WRB(CSB) rising
-1
-
-
ns
tCS
CSB(WRB) input setup time before WRB(CSB) falling
0
-
-
ns
tCH
CSB(WRB) input hold time after WRB(CSB) rising
0
-
-
ns
tWW
WRB(CSB) active time width
40
-
-
ns
tWAIT Wait time from WRB(CSB) rising to the next WRB(CSB) or to RDB falling
30
-
-
ns
tDS
Data setup time before WRB(CSB) rising
35
-
-
ns
tDH
Data hold time after WRB(CSB) rising
-1
-
-
ns
＊Regulation all at threshold of VDDIO1×1/2 (VDD=1.50V,VDDIO=2.85V,GND=0.0V,Ta=25ºC)
＊It is possible to use it with either CSB or WRB active. However, either of them must do LOW pulse operation.
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9/16
2009.04 - Rev.B