BU6566GVW_09 Datasheet, PDF (11/17 Pages) Rohm – Camera Image Processors Compatible with JPEG Image

BU6566GVW, BU6568GV
Technical Note
2. Camera Module Interface Timing
2.1. System clock and camera clock
External input clock (XIN) may be divided set and supplied as CAMCKO clock to camera module.
The relation of data synchronization clock CAMCKI clock from camera and system clock SCLK must be set so as to meet the
following formula.
fSCLK  2 × fCAMCKI
……(2.1-1)
fSCLK
System clock frequency
fCAMCKI
Camera clock frequency input to CAMCKI terminal
Moreover, [Camera timing 1] or [Camera timing 2] shown below must be satisfied.
[Camera timing１] (In the case when CAMCKI signal is as asynchronous as CAMCKO)
tCAMCKIH > tSCLK + 1ns and tCAMCKIL > tSCLK + 1ns ……(2.1-2)
tCAMCKIH
CAMCKI High interval
tCAMCKIL
CAMCKI Low interval
[Camera timing 2] (In the case when CAMCKI signal is as synchronous as CAMCKO)
total delay + margin ( 10ns) < tSCLK
……(2.1-3)
total delay
delay from CAMCKO change point to CAMCKI change point
The clock relation in fSCLK = fCAMCKO = 2 × fCAMCKI is shown in Figure.2.1-1.
[fSCLK=fCAMCKO=2 × fCAMCKI]
internal SCLK
CAMCKO
CAMCKI
total delay
detect
CAMCKI = "H"
CAMCKO
detect
CAMCKI = "L"
BU6566GVW _total
delay
/BU6568GV
CAMCKI
CAMERA
Module
Figure .2.1-1 Relation between system clock and camera clock
2.2. Camera module interface timing
The timing of the camera image signal in camera I/F is shown in Table 2.2-1.
CAMVS
CAMHS
CAMD0
－CAMD7
CAMCKI
(CKPL=“0”)
CAMCKI
(CKPOL=“1”)
tCMS
tCMH
Table 2.2-1 BU6566GVW/BU6568GV timing (camera data)
Symbol
Details
MIN. TYP. MAX. Unit
tCMS CAMCKI rising/falling camera set up time
1/5 -
-
ns
tCMH CAMCKI rising/falling camera hold time
1/5 -
-
ns
Remarks
BU6566GVW/BU6568GV
BU6566GVW/BU6568GV
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© 2009 ROHM Co., Ltd. All rights reserved.
11/16
2009.04 - Rev.B