BU6566GVW_09 Datasheet, PDF (10/17 Pages) Rohm – Camera Image Processors Compatible with JPEG Image

BU6566GVW, BU6568GV
Technical Note
Table 1.2-2 BU6568GV timing conditions（RAM, register write cycle）
Symbol
Details
MIN. TYP. MAX Unit
tWC
Write cycle time
55
-
-
ns
tAS
Address setup time before WRB(CSB) falling
-4
-
-
ns
tAH
Address hold time after WRB(CSB) rising
0
-
-
ns
tCS
CSB(WRB) input setup time before WRB(CSB) falling
0
-
-
ns
tCH
CSB(WRB) input hold time after WRB(CSB) rising
0
-
-
ns
tWW
WRB(CSB) active time width
40
-
-
ns
tWAIT
Wait time from WRB(CSB) rising to the next WRB(CSB) or to RDB falling
15
-
-
ns
tDS
Data setup time before WRB(CSB) rising
30
-
-
ns
tDH
Data hold time after WRB(CSB) rising
0
-
-
ns
＊Regulation all at threshold of VDDIO1×1/2 (VDD=1.50V,VDDIO=2.85V,GND=0.0V,Ta=25ºC)
＊It is possible to use it with either CSB or WRB active. However, either of them must do LOW pulse operation.
1.3 Register (including RAM via register) read timing.
A2,A1
tAS
tRC
tAH
CSB（RDB）
WRB
Address Input
tCS
tRD
tCH
RDB（CSB）
tWAIT
D[15:0]
tROE
Read Data
tROD
Table 1.3-1 BU6566GVW timing conditions (RAM, register read cycle)
Symbol
Details
MIN. TYP. MAX. Unit
tRC
Read cycle time
100
-
-
ns
tAS
Address setup time before RDB(CSB) falling
-5
-
-
ns
tAH
Address hold time after RDB(CSB) rising
-1
-
-
ns
tCS
CSB(RDB) input setup time before RDB(CSB) falling
0
-
-
ns
tCH
CSB(RDB) input hold time after RDB(CSB) rising
0
-
-
ns
tRD
Access time after RDB(CSB) falling
-
-
70
ns
tWAIT
Wait time from RDB(CSB) rising to the next RDB(CSB) falling or to WRB falling
30
-
-
ns
tROE,tROD
Data output enable time after RDB(CSB) falling, Data output disable time after RDB(CSB) rising
-
-
15
ns
＊Regulation all at threshold of VDDIO1×1/2 (VDD=1.50V,VDDIO=2.85V,GND=0.0V,Ta=25ºC)
＊It is possible to use it with either CSB or RDB active. However, either of them must do LOW pulse operation.
Table 1.3-2 BU6568GV timing conditions (RAM, register read cycle)
Symbol
Details
MIN. TYP. MAX. Unit
tRC
Read cycle time
74.5
-
-
ns
tAS
Address setup time before RDB(CSB) falling
-4
-
-
ns
tAH
Address hold time after RDB(CSB) rising
0
-
-
ns
tCS
CSB(RDB) input setup time before RDB(CSB) falling
0
-
-
ns
tCH
CSB(RDB) input hold time after RDB(CSB) rising
0
-
-
ns
tRD
Access time after RDB(CSB) falling
-
-
70
ns
tWAIT
Wait time from RDB(CSB) rising to the next RDB(CSB) falling or to WRB falling
30
-
-
ns
tROE,tROD
Data output enable time after RDB(CSB) falling, Data output disable time after RDB(CSB) rising
8
-
-
ns
＊Regulation all at threshold of VDDIO1×1/2 (VDD=1.50V,VDDIO=2.85V,GND=0.0V,Ta=25ºC)
＊It is possible to use it with either CSB or RDB active. However, either of them must do LOW pulse operation.
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10/16
2009.04 - Rev.B