BU6566GVW_09 Datasheet, PDF (12/17 Pages) Rohm – Camera Image Processors Compatible with JPEG Image

BU6566GVW, BU6568GV
Technical Note
3. LCD direct access
When to set up with A2="L", direct access to LCD module is set up, and HOST CPU signal penetrated to LCD signal.
CSB
LCDCSB
WRB
LCDWRB
RDB
LCDRDB
A1
LCDA0
D0～D15
LCDD0～LCDD15
tCSf1
tWRf1
tWRr1
tAD1
tDTw1
tCSr1
tRDf1
tAD2
tDTr1
tRDr1
Table 3-1 BU6566GVW timing conditions（LCD direct access）
Symbol
Details
MIN.
TYP.
MAX.
Unit
tCSf1 Delay from CSB to LCDCSB falling
3.5
-
12.0
ns
tCSr1 Delay from CSB to LCDCSB rising
2.1
-
9.3
ns
tWRf1 Delay from WRB to LCDWRB falling
3.0
-
11.2
ns
tWRr1 Delay from WRB to LCDWRB rising
2.0
-
9.2
ns
tRDf1 Delay from RDB to LCDRDB falling
3.0
-
11.8
ns
tRDr1 Delay from RDB to LCDRDB rising
2.0
-
9.1
ns
tAD1
Delay from A1 to LCDA0
1.8
-
9.6
ns
tDTw1 Delay from D0～D15 to LCDD0～LCDD15
7.4
-
22.3
ns
tDTr1 Delay from LCDD0～LCDD15 to D0～D15
3.0
-
13.35
ns
Table 3-2 BU6568GV timing conditions（LCD direct access）
Symbol
Details
MIN.
TYP.
MAX.
Unit
tCSf1 Delay from CSB to LCDCSB falling
3.0
-
12.0
ns
tCSr1 Delay from CSB to LCDCSB rising
2.5
-
10.0
ns
tWRf1 Delay from WRB to LCDWRB falling
3.0
-
12.0
ns
tWRr1 Delay from WRB to LCDWRB rising
2.5
-
10.0
ns
tRDf1 Delay from RDB to LCDRDB falling
3.0
-
12.0
ns
tRDr1 Delay from RDB to LCDRDB rising
2.5
-
10.0
ns
tAD1
Delay from A1 to LCDA0
2.5
-
10.0
ns
tAD2
Delay from A1 to LCDA0
6.0
24.0
ns
tDTw1 Delay from D0～D15 to LCDD0～LCDD15
4.0
-
16.0
ns
tDTr1 Delay from LCDD0～LCDD15 to D0～D15
4.0
-
16.0
ns
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12/16
2009.04 - Rev.B