BD95513MUV_10 Datasheet, PDF (9/18 Pages) Rohm – Switching Regulator with MOS FET for DDR-SDRAM Cores

BD95513MUV
Technical Note
●Pin Descriptions
・V_CC
This pin supplies power to the IC’s internal circuitry, excluding the FET driver. The input supply voltage range is
4.5 to 5.5V, with a maximum current draw of 900µA. This pin should be bypassed with a capacitance of approximately 0.1µF.
・EN
Enables or disables the switching regulator. When the voltage on this pin reaches 2.3 V or higher, the internal switching
regulator is turned on. At voltages less than 0.8 V, the regulator is turned off.
・V_DD
This pin supplies power to the low side of the FET driver, as well as to the bootstrap diode. As the diode draws its peak
current when switching on or off, this pin should be bypassed with a capacitance of approximately 1 µF.
・V_REG
Output pin from the 5 V linear regulator. This pin also supplies power to the internal driver and control circuitry.
V_REG standby function is controlled by the CTL pin. The output supplies 5V at 100 mA and should be bypassed to ground
using a 10 µF capacitor with a rating of X5R or X7R.
・EXTV_CC
External power supply input for the linear regulator. When the voltage on the EXTV_CC pin exceeds 4.4 V, the regulator
uses it in conjunction with other power sources to supply V_REG. Leave the EXTV_CC pin floating when not in use.
・REF
Reference voltage output pin. The reference voltage is set internally by the IC to 0.7 V, and the IC works to keep V_REF
approximately equal to V_FB. Variations in voltage levels on this pin affect the output voltage, so the pin should be
bypassed with a 100 pF ~ 0.1 µF ceramic capacitor.
・SS
Soft start/stop pin. When EN is set high, the capacitor between the internal current source and SS-GND controls the
startup time of the IC. When the voltage on the SS pin is lower than the REF output voltage (0.7 V), the output voltage is
held at the same voltage as the SS pin.
・AV_IN
The BD95513MUV controls the duty cycle and output voltage based upon the input voltage at this pin, so voltage
variations or oscillations on this line can cause operation to become unstable. This pin also acts as the voltage input for
the switching block, so insufficient coupling impedance can also cause operation to become unstable. Therefore, this
line should be bypassed with either a power capacitor or RC filter.
・FS
Frequency-adjusting resistance input pin. Attaching a resistance of 30 k ~ 100 kΩ adjusts the switching frequency from
200 kHz ~ 1 MHz.
・BOOT
This pin serves as the power source for the high side of the FET driver. A bootstrap diode is integrated within the IC.
The maximum voltage on this pin should not exceed +30 V vs. GND or +7 V vs. SW. When operating the switching
regulator, the operation of the bootstrap circuitry causes the BOOT voltage to swing from (V_IN + V_DD) ~ V_DD.
・PGOOD
Power good indicator. This open-drain output should be connected via a 100 kΩ pull-up resistor.
・MODE
Mode selection pin. When low, the IC functions in forced-continuous mode; at voltages from 0V ~ 3V, QLLM mode; when
high, SLLM^TM mode.
・CTL
Linear regulator control pin. When voltage is 2.3 V or higher, a logic HIGH is recognized and the internal regulator
(V_REG = 5 V) is switched on. At voltages of 0.8 V or lower, a logic LOW is recognized and the regulator is switched off.
However, even if EN is logic HIGH, the switching regulator will not operate if CTL is logic LOW.
・FB
Output voltage feedback input. V_FB is held at 0.7 V by the IC.
・SW
Output from the switching regulator to the inductor. This output swings from V_IN ~ GND. The trace from the output to
the inductor should be as short and wide as possible.
・V_OUT
Voltage output discharge pin. When EN is off, this output is pulled low.
・V_IN
Power supply input. The IC can accept any input from 4.5 V to 28 V. This pin should be bypassed directly to ground by
a power capacitor.
・PGND
Power ground terminal.
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2010.10- Rev.A