BU9833GUL-W Datasheet, PDF (7/13 Pages) Rohm – Silicon Monolithic Integrated Circuit

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◇WP TIMING
SCL
DATA(1)
SDA
D1
D0 _ACK
WP
DATA(n)
ACK
ｔＷＲ
STOP BIT
tSU：WP
Fig-6(a) WP TIMING OF THE WRITE OPERATION
ｔＨＤ：WP
SCL
DATA(1)
DATA(n)
SDA ^D1
D0 _ACK
tHIGH:WP
ACK
WP
Fig-6(b) WP TIMING OF THE WRITE CANCEL OPERATION
○For the WRITE operation, WP must be "LOW" during the period of time from the rising edge of
the clock which takes in D0 of first byte until the end of tWR. ( See Fig-6(a) )
During this period, WRITE operation is canceled by setting WP "HIGH".（ See Fig-6(b) ）
○In the case of setting WP "HIGH" during tWR, WRITE operation is stopped in the middle and the
data of accessing address is not guaranteed. Please write correct data again in the case.
◇DEVICE OPERATION
REV. A