BU97530KVT Datasheet, PDF (51/59 Pages) Rohm – Built-in OSC circuit

BU97530KVT
Datasheet
Voltage Detection Type Reset Circuit (VDET)
The Voltage Detection Type Reset Circuit generates an output signal that resets the system when power is applied for
the first time and when the power supply voltage drops (that is, for example, the power supply voltage is less than or equal to
the power down detection voltage (VDET = 1.8V typ.). To ensure that this reset function works properly, it is recommended that
a capacitor be connected to the power supply line so that both the power supply voltage (VDD) rise time when power is first
applied and the power supply voltage (VDD) fall time when the voltage drops are at least 1ms.
t1
t2
VDD
Figure 39. VDET Detection Timing
Power supply voltage VDD rise time: t1 > 1ms
Power supply voltage VDD fall time: t2 > 1ms
RESET CONDITION
When BU97530KVT is initialized, the internal status after power supply has been reset as the following table.
Instruction
Key Scan mode
S1/P1/G1 to S9/P9/G9 pin
Inversion mode
LCD bias
LCD duty
DISPLAY frequency
Display clock mode
LCD display
Power mode
PWM/GPO output
PWM frequency
PWM duty
Display Contrast setting
At Reset Condition
[KM0,KM1,KM2]=[1,1,1]:Keyscan no use
[P0,P1,P2,P3]=[0,0,0,0]:all segment output
FL=0:Line Inversion
DR=0:1/3 bias
[DT0,DT1]=[1,0]:1/4 duty
[FC0,FC1,FC2,FC3]=[0,0,0]:fosc/12288
OC=0:Internal oscillator
SC=1:OFF
[BU0, BU1, BU2]=[1,1,1]:Power saving mode
PGx=0:PWM output(x=1～9)
[PF0,PF1,PF2,PF3]=[0,0,0,0]: fosc /4096
[Wn1～Wn8]=[0,0,0,0,0,0,0,0]:0/256)xTp
(n=1～9,Tp=1/fp)
[CT0,CT1,CT2,CT3]=[0,0,0,0]:VLCD Level is
1.00*VDD
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TSZ02201-0P4P0D300570-1-2
02.Mar.2015 Rev.003