BU97530KVT Datasheet, PDF (5/59 Pages) Rohm – Built-in OSC circuit

BU97530KVT
Datasheet
MPU Interface Characteristics (Ta = -40 to +85°C, VDD = 2.7V to 6.0V, VSS = 0.0V)
Parameter
Symbol
Pin
Conditions
Min
Limit
Typ
Max
Unit
Data Setup Time
tds SCL, SDI
120
-
-
ns
Data Hold Time
tdh SCL, SDI
120
-
-
ns
SCE Wait Time
tcp SCE, SCL
120
-
-
ns
SCE Setup Time
tcs SCE, SCL
120
-
-
ns
SCE Hold Time
tch SCE, SCL
120
-
-
ns
Clock Cycle Time
tccyc SCL
320
-
-
ns
High-level Clock Pulse
Width
tchw SCL
120
-
-
ns
Low-level Clock Pulse
Width (Write)
tclww SCL
120
-
-
ns
Low-Level Clock Pulse
Width (Read)
tclwr SCL
RPU=4.7KΩ
CL=10pF^(Note4)
1.6
-
-
us
Rise Time
tr SCE, SCL, SDI
-
160
-
ns
Fall Time
tf
SCE, SCL, SDI
-
160
-
ns
SDO Output Delay
Time
tdc SDO
RPU=4.7KΩ
CL=10pf^(Note4)
-
-
1.5
µs
SDO Rise Time
tdr SDO
RPU=4.7KΩ
CL=10pf^(Note4)
-
-
1.5
µs
(Note4) Since SDO is an open-drain output, “tdc” and “tdr” depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
RPU: 1kΩ≤RPU≤10kΩ is recommended.
CL: A parasitic capacitance to VSS in an application circuit. Any component is not necessary to be attached.
Power supply for I/O level
SDO
R_PU
Host
C_L
1. When SCL is stopped at the low level
SCE
SCL
SDI
SDO
VIH1, VIH2
VIL1
tccyc
tchw
tclww
tr
tf
VIH1, VIH2
VIL1
tds
tdh
2. When SCL is stopped at the high level
SCE
VIH1,VIH2
SCL
VIL1
tccyc
tclww
tchw
tf
tr
SDI
VIH1,VIH2
VIL1
SDO
tds
tdh
VIH1, VIH2
tcs
tclwr
VIL1
tch
VIH1, VIH2
tclwr
tcp
VOL5
tdc
tdr
VIL1
tch
VOL5
tdc
tdr
Figure 5.Serial Interface Timing
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02.Mar.2015 Rev.003