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BU94601KV_12 Datasheet, PDF (19/70 Pages) Rohm – AAC/WMA/MP3 +SD Memory Card + iPod
BU94601KV BU94603KV BU94604BKV
Datasheet
Step1
S Slave Address R/W A Data(8bit) A
Data(8bit) A/A P
Step2
"0"(write)
S Slave Address R/W A Data(8bit) A Data(8bit) A
Data(8bit)
"1"(read)
From Master to Slave
A = Acknowledge(SDA low)
From Slave to Master
A = No Acknowledge(SDA high)
S = Start Condition
P = Stop condition
Figure 13 Status Reception Protocol
A/A P
I2C Step1 command
BUSY
S Slave Address R A
0xFF
A Data(8bit) A
Dummy byte for Busy
Data(8bit) A/A P
Step1 command
S Slave Address R A
0x00
A Data(8bit) A
Dummy byte for Busy
Data(8bit) A/A P
Figure 14 Relationship between Transfer Data and BUSY
11.5 I2C Bus line electrical specification and timing
SDA and SCL bus-line characteristic (Unless specified, Ta=25℃, VDD1=3.3V)
Parameter
Code
Min.
Max.
Unit
1 SDA, SCL H input voltage
VIH
VDD*0.7
VDD
V
2 SDA, SCL L input voltage
VIL
DVSS
VDD*0.3
V
3 SDA H output voltage
VOH
VDD-0.4
VDD
V
4 SDA L output voltage
VOL
0
0.4
V
5 SCL clock frequency
fSCL
0
400
kHz
Bus-free-time between "Stop" condition and
6
tBUF
1.3
"Start" condition
-
us
Hold time for "Start" condition
7
After this, the first clock pulse is generated.
tHD;STA
0.6
-
us
8 LOW status hold-time of SCL clock
tLOW
1.3
-
us
9 HIGH status hold-time of SCL clock
tHIGH
0.6
-
us
10 Data-hold-time
tHD;DAT
0*
-
us
11 Date-setup-time
tSU;DAT
100
-
ns
12 Rising time of SDA and SCL signal
tR
20+0.1*Cb
300
ns
13 Fall time of SDA and SCL signal
tF
20+0.1*Cb
300
ns
14 Setup time of "Stop" condition
tSU;STO
0.6
-
us
15 Capacitive load of each bus-line
Cb
-
400
pF
The above-mentioned numerical values are all the values corresponding to VIH min and VIL max level.
*To exceed an undefined area on falling edged of SCL, transmission device should internally offer the hold-time of 300ns or more for SDA signal (VIH min of
SCL signal).
Because the "Repeated Start" condition to send "Start" condition without sending "Stop" condition doesn't correspond, after sending "Start" condition, always
send "Stop" condition.
Neither terminal SCL nor terminal SDA correspond to 5V tolerant.
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2012.07.12 Rev.001