DS1650 Datasheet, PDF (9/26 Pages) National Semiconductor (TI) – Quad Differential Line Receivers

Parameter
Symbol
Test Conditions
COM Outputs
COM1, COM2 N-FET
On-Resistance
RON_COM
VRECT = 2.6V
COM1, COM2 Signaling
Frequency
COM1, COM2 Leakage
Current
fCOM
ICOM_LKG
VCOM1 = VCOM2 = 20V
CLAMP Outputs
CLMP1, CLMP2 N-FET
On-Resistance
RON_CLM
Adapter Power Enable Control
ADD Detection Voltage
Threshold
ADD Detection Voltage
Hysteresis
VADD
VADD Rising : 0V  5V
VADD Falling : 5V  0V
ADD Input Leakage Current IADD_LKG
Pull-up Resistance from ADEN
to OUT pin when Adapter
RADD
mode is disabled
VADD = 5V , VRECT = 0V
VADD = 0V, VOUT = 5V
ADD to ADEN Voltage when
Adapter Mode is Enabled
VAD_EN
VADD = 5V, VADD – VADEN
GPIO Input/Output
GPIO Input Voltage
(Logic-Low)
VIL
GPIO Input Voltage
(Logic-High)
VIH
GPIO Output Voltage
(Logic-Low)
VOL
GPIO Output Voltage
(Logic-High)
VOH
Received Power (WPC Related Measurements)
Received Power Accuracy
PRX_AC
I²C Compatible Interface (Note 5)
IOUT = 0A to 1A (Note 5)
Logic Input (SDA, SCL) Low
Level
VSCL_L
Logic Input (SDA, SCL) High
Level
VSCL_H
SCL Clock Frequency
fCLK
Output Fall Time
tFL2COUT
Bus Free Time Between
Stop/Start
tBUF
Hold Time Start Condition
tHD_STA
Setup Time for Start Condition tSU_STA
RT1650
Min Typ Max Unit
-- 0.7 --

--
2
-- kHz
--
--
1 A
-- 0.5 --

3 3.6 4
V
-- 400 -- mV
--
-- 60 A
-- 275 350 
3 4.25 5
V
0
-- 0.8 V
2
--
5
V
--
-- 0.4 V
2.6 3.3 3.6 V
--
-- 0.25 W
--
-- 0.6 V
1.2 --
--
V
10 -- 400 kHz
--
-- 250 ns
1.3 --
-- s
0.6 --
0.6 --
-- s
-- s
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DS1650-00 July 2015
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