DS1650 Datasheet, PDF (25/26 Pages) National Semiconductor (TI) – Quad Differential Line Receivers

Power trace should be as short and
wide as possible.
RX2
RX1
RT1650
GND
VOUT
CRECT1
CRECT2
CD1
CD2
CBOOT2
CBOOT1
BOOT2 PGND PGND PGND PGND BOOT1
AC2 AC2 AC2 AC1 AC1 AC1
RECT RECT RECT RECT RECT COM1
OUT OUT OUT OUT OUT CLMP1
PGND NC
NC VDD1 VDD2 COM2
SCL SDA GPIO VDD1 VDD2 CLMP2
TS MODE0 MODE1 NC
NC PGND
CHG ADEN ADD PGND PGND PGND
Power ground should be as large
as possible and connect to the
ground plane for thermal
dissipation.
Figure 17. PCB Layout Guide
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DS1650-00 July 2015
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