DS1650 Datasheet, PDF (10/26 Pages) National Semiconductor (TI) – Quad Differential Line Receivers

RT1650
Parameter
Symbol
Test Conditions
Min Typ Max Unit
SCL Low Time
tLOW
1.3 --
-- s
SCL High Time
tHIGH
0.6 --
-- s
Data Setup Time
tSU_DAT
100 --
--
ns
Data Hold Time
tHD_DAT
0
-- 900 ns
Setup Time for Stop Condition tSU_STO
0.6 --
-- s
Mode Control
Logic Input (MODE0, MODE1)
Low Level
VMODE_L
--
-- 0.6 V
Logic Input (MODE0, MODE1)
High Level
VMODE_H
1.2 --
--
V
Communication Interface
FSK Modulation Frequency
Change
fFSK
fOP = 175kHz (Note 5)
3
5
7 kHz
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Specification is guaranteed by design and/or correlation with statistical process control.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS1650-00 July 2015