DS1650 Datasheet, PDF (18/26 Pages) National Semiconductor (TI) – Quad Differential Line Receivers

RT1650
35
30
25
20
15
10
5
0
-50 -25
0 25 50 75 100 125 150
Temperature (degree-C)
Figure 8. Equivalent Resistance for Temperature
Sensing
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50 -25
0 25 50 75 100 125 150
Temperature (°C)
Figure 9. Thermal Sensing Voltage
Communication
The RT1650 supports two communication modulations,
Amplitude Shift Keying (ASK), Frequency Shift Keying
(FSK), to communicate with the power transmitter. For
ASK modulation, the RT1650 provides two integrated
communication N-FETs which are connected to the
COM1 and COM2 pins. These N-FETs are used for
modulating the secondary load current which allows the
RT1650 to communicate Control Error and
configuration information to the transmitter. Figure 10
shows the RT1650 operating with capacitive load
modulation. When the N-FETs are turned-on, there is
effectively a capacitor connected between AC1 and
AC2. The impedance seen by the coil will be reflected
in the primary as a change in current.
C_S
AC1
C_com
Coil
C_d
COM1
COM2
C_com
AC2
Figure 10. Capacitive Load Modulation
The RT1650 supports FSK demodulation to receive the
power signal from the transmitter shown as Figure 11.
The change in frequency between high and low states
is dependent on the operating frequency. The power
transmitter should modulate the power signal at
specific times during the Negotiation phase to avoid
interrupting communication packets from the receiver.
The FSK modulation scheme should be compliant with
WPC Volume II V0.9.
Figure 11. FSK Modulation Power Signal
Bit Encoding Scheme
According to WPC protocol, the RT1650 uses a
differential bi-phase encoding scheme to modulate
data bits onto the Power Signal. The internal clock
signal has a frequency 2kHz. The Receiver shall
encode a ONE bit using two transitions in the Power
Signal, such that the first transition coincides with the
rising edge of the clock signal, and the second
transition coincides with the falling edge of the clock
signal. The Receiver shall encode a ZERO bit using a
single transition in the Power Signal, which coincides
with the rising edge of the clock signal. Figure 12
shows an example of the differential bi-phase encoding.
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DS1650-00 July 2015