H8S2646 Datasheet, PDF (927/1165 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

IRR—Interrupt Register
Appendix B Internal I/O Register
H'F812
HCAN
Bit
Initial value
Read/Write
15
IRR7
0
R/(W)*
14
IRR6
0
R/(W)*
13
IRR5
0
R/(W)*
12
IRR4
0
R/(W)*
11
IRR3
0
R/(W)*
10
IRR2
0
R/(W)*
9
IRR1
0
R/(W)*
8
IRR0
1
R/(W)*
Reset Interrupt Flag
0 [Clearing condition]
Writing 1
1 Transition to hardware reset (HCAN module stop, software
standby)
[Setting condition]
When reset processing is completed after hardware reset
transition (HCAN module stop, software standby)
Note: After canceling a reset or returning from hardware standby
mode, the module stop bit is initialized yo 1. HCAN then
enters a module-stopped state.
Receive Message Interrupt Flag
0 [Clearing condition]
Clearing of all bits in RXPR (receive complete register) in the mailbox,
which enables the receive interrupt requests in MBIMR
1 Data frame or remote frame received and stored in mailbox
[Setting conditions]
When data frame or remote frame reception is completed, when
corresponding MBIMR = 0
Remote Frame Request Interrupt Flag
0 [Clearing condition]
Clearing of all bits in RFPR (remote request wait register) in the mailbox,
which enables the receive interrupt requests in MBIMR
1 Remote frame received and stored in mailbox
[Setting conditions]
When remote frame reception is completed, when corresponding MBIMR = 0
Transmit Overload Warning Interrupt Flag
0 [Clearing condition]
Writing 1
1 Error warning state caused by transmit error
[Setting condition]
When TEC ≥ 96
Receive Overload Warning Interrupt Flag
0 [Clearing condition]
Writing 1
1 Error warning state caused by receive error
[Setting condition]
When REC ≥ 96
Bus Off Interrupt Flag
0 [Clearing condition]
Writing 1
1 Bus off state caused by transmit error
[Setting condition]
When TEC ≥ 256
Overload Frame Interrupt Flag
0 [Clearing condition]
Writing 1
1 Overload frame transmission
[Setting conditions]
When overload frame is transmitted
Error Passive Interrupt Flag
0 [Clearing condition]
Writing 1
1 Error passive state caused by transmit/receive error
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
Note: * Only 1 can be written, to clear the flag.
Rev. 5.00 Sep 22, 2005 page 901 of 1136
REJ09B0257-0500