H8S2646 Datasheet, PDF (454/1165 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Watchdog Timer
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
see section 12.2.4, Notes on Register Access.
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF
0
1
Description
[Clearing condition]
(Initial value)
Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the
H8S/2646 Group if TCNT overflows during watchdog timer operation.
Bit 6
RSTE
Description
0
Reset signal is not generated if TCNT overflows^*
(Initial value)
1
Reset signal is generated if TCNT overflows
Note: * The modules within the H8S/2646 Group are not reset, but TCNT and TCSR within the
WDT are reset.
Bit 5—Reserved: Always read as 0. Can only be written with 0.
Bits 4 to 0—Reserved: Always read as 1. Not writable.
Rev. 5.00 Sep 22, 2005 page 428 of 1136
REJ09B0257-0500