H8S2646 Datasheet, PDF (460/1165 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Watchdog Timer
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. If
TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated
for the entire H8S/2646 Group chip. Figure 12.7 shows the timing in this case.
φ
TCNT
Overflow signal
(internal signal)
WOVF
Internal reset
signal
H'FF
H'00
518 states (WDT0)
515/516 states (WDT1)
Figure 12.7 Timing of Setting of WOVF
Rev. 5.00 Sep 22, 2005 page 434 of 1136
REJ09B0257-0500