H8S2646 Datasheet, PDF (1056/1165 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
TIOR0L—Timer I/O Control Register 0L
H'FF13
TPU0
Bit
Initial value
Read/Write
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
TGR0C I/O Control
00
0 0 TGR0C is Output disabled
1 ^output
Initial output is 0
1
0
compare
register^*1
output
1
0 output at compare match
1 output at compare match
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR0C is Capture input
Input capture at rising edge
1 ^input
source is
capture TIOCC0 pin
1 * _register*1
Input capture at falling edge
Input capture at both edges
1* *
Capture input Input capture at TCNT1 count-up/
source is channel count-down
1/count clock
*: Don't care
Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
TGR0D I/O Control
0 0 0 0 TGR0D is Output disabled
1 ^output
Initial output is 0
1
0
compare
register^*2
output
1
100
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR0D is Capture input
Input capture at rising edge
1 ^input
source is
capture TIOCD0 pin
1 * _register*2
Input capture at falling edge
Input capture at both edges
1* *
Capture input Input capture at TCNT1 count-up/
source is channel count-down^*1
1/count clock
*: Don't care
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the
TCNT1 count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
Rev. 5.00 Sep 22, 2005 page 1030 of 1136
REJ09B0257-0500