H8S2114R Datasheet, PDF (909/1038 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 24 Power-Down Modes
Bit Bit Name Initial Value R/W
6 STS2 0
R/W
5 STS1 0
R/W
4 STS0 0
R/W
3
0
R/W
2 SCK2 0
R/W
1 SCK1 0
R/W
0 SCK0 0
R/W
[Legend]
X:
Don't care
Description
Standby Timer Select 2 to 0
On canceling software standby mode, watch mode, or
subactive mode, these bits select the wait time for clock
stabilization from clock oscillation start. Select a wait time
of 8 ms (oscillation stabilization time) or more, depending
on the operating frequency. Table 24.1 shows the
relationship between the STS2 to STS0 values and wait
time.
With an external clock, an arbitrary wait time can be
selected. For normal cases, the minimum value is
recommended.
Reserved
The initial value should not be changed.
System Clock Select 2 to 0
These bits select a clock for the bus master in high-speed
mode or medium-speed mode.
When making a transition to subactive mode or watch
mode, these bits must be cleared to B'000.
000: High-speed mode
001: Medium-speed clock: φ/2
010: Medium-speed clock: φ/4
011: Medium-speed clock: φ/8
100: Medium-speed clock: φ/16
101: Medium-speed clock: φ/32
11X: Setting prohibited
Rev. 3.00 Jul. 14, 2005 Page 861 of 986
REJ09B0098-0300