H8S2114R Datasheet, PDF (189/1038 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 7 Data Transfer Controller (DTC)
7.2.7 DTC Enable Registers (DTCER)
DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers:
DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in
tables 7.1 and 7.2. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by
masking all interrupts and writing data after executing a dummy read on the relevant register.
Bit Bit Name Initial Value R/W Description
7 DTCEn7 0
R/W DTC Activation Enable
6 DTCEn6 0
5 DTCEn5 0
4 DTCEn4 0
3 DTCEn3 0
2 DTCEn2 0
1 DTCEn1 0
0 DTCEn0 0
R/W Setting this bit to 1 specifies a relevant interrupt source
R/W ^{as a DTC activation source.}
R/W ^{[Clearing conditions]}
R/W ^{• When data transfer has ended with the DISEL bit in}
R/W
MRB set to 1
R/W ^{• When the specified number of transfers have}
ended
R/W
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not been
completed
Note: n: A to E
Table 7.1 Correspondence between Interrupt Sources and DTCER
Bit Bit Name DTCERA
7 DTCEn7 (16)IRQ0
6 DTCEn6 (17)IRQ1
5 DTCEn5 (18)IRQ2
4 DTCEn4 (19)IRQ3
3 DTCEn3 (28)ADI
2 DTCEn2 (48)ICIA
1 DTCEn1 (49)ICIB
0 DTCEn0 (52)OCIA
Note: n : A to E
( ) : Vector number
DTCERB
(53)OCIB
(39)TGI1A
(40)TGI1B
(43)TGI2A
(44)TGI2B
(64)CMIA0
(65)CMIB0
(68)CMIA1
Register
DTCERC
(69)CMIB1
(72)CMIAY
(73)CMIBY
(76)CMIAX
(77)CMIBX


(85)RXI1
DTCERD
(86)TXI1
(89)RXI2
(90)TXI2
(92)IICI0
(94)IICI1



DTCERE
(34)TGI0A
(35)TGI0B
(36)TGI0C
(37)TGI0D
(108)ERR1
(109)IBFI1
(110)IBFI2
(111)IBFI3
Rev. 3.00 Jul. 14, 2005 Page 141 of 986
REJ09B0098-0300