H8S2114R Datasheet, PDF (425/1038 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 13 8-Bit Timer (TMR)
Section 13 8-Bit Timer (TMR)
This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, and TMR_X) with four
channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a
multifunction timer in a variety of applications, such as generation of counter reset, interrupt
requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two
registers.
13.1 Features
• Selection of clock sources
The counter input clock can be selected from six internal clocks and an external clock
• Selection of three ways to clear the counters
The counters can be cleared on compare-match A, compare-match B, or by an external reset
signal.
• Timer output controlled by two compare-match signals
The timer output signal in each channel is controlled by two independent compare-match
signals, enabling the timer to be used for various applications, such as the generation of pulse
output or PWM output with an arbitrary duty cycle.
• Cascading of two channels
 Cascading of TMR_0 and TMR_1
Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1
as the lower half (16-bit count mode).
TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count
mode).
 Cascading of TMR_Y and TMR_X
Operation as a 16-bit timer can be performed using TMR_Y as the upper half and TMR_X
as the lower half (16-bit count mode).
TMR_X can be used to count TMR_Y compare-match occurrences (compare-match count
mode).
• Multiple interrupt sources for each channel
TMR_0, TMR_1, and TMR_Y: Three types of interrupts: Compare-match A, compare-
match B, and overflow
TMR_X: Four types of interrupts: Compare-match A, compare match B,
overflow, and input capture
TIMH265A_000020020800
Rev. 3.00 Jul. 14, 2005 Page 377 of 986
REJ09B0098-0300