R1EX25002ASA00A Datasheet, PDF (9/22 Pages) Renesas Technology Corp – Serial Peripheral Interface Electrically Erasable and Programmable Read Only Memory

R1EX25002Axx00A/R1EX25004Axx00A
Functional Description
Status Register
The following figure shows the Status Register Format. The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific instructions.
Status Register Format
b7
b0
1
1
1
1
BP1 BP0 WEL WIP
Block Protect Bits
Write Enable Latch Bits
Write In Progress Bits
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be protected
against Write instructions.
Instructions
Each instruction starts with a single-byte code, as summarized in the following table . If an invalid instruction is sent
(one not contained in the following table), the device automatically deselects itself.
Instruction Set
Instruction
Description
WREN
Write Enable
WRDI
Write Disable
RDSR
Read Status Register
WRSR
Write Status Register
READ
Read from Memory Array
WRITE
Write to Memory Array
Notes: 1. “×” is Don’t care.
2. “A” is A₈ address on the R1EX25004A, and Don’t care on the R1EX25002A.
Instruction Format
0000 ×110
0000 ×100
0000 ×101
0000 ×001
0000 A011
0000 A010
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
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