R1EX25002ASA00A Datasheet, PDF (13/22 Pages) Renesas Technology Corp – Serial Peripheral Interface Electrically Erasable and Programmable Read Only Memory

R1EX25002Axx00A/R1EX25004Axx00A
Write Status Register (WRSR):
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded and executed, the device sets the Write Enable Latch(WEL). The instruction sequence is
shown in the following figure. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of
the Status Register. b6, b5 and b4 are always read as 0. Chip select (S) must be driven high after the rising edge of
serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as chip select (S) is driven high, the
self-timed Write Status Register cycle (whose duration is t_W) is initiated. While the Write Status Register cycle is in
progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In
Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, Write Enable Latch(WEL) is reset. The Write Status Register (WRSR) instruction allows the user
to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only,
as defined in the Status Register Format table.
The contents of Block Protect (BP1, BP0) bits are frozen at their current values just before the start of the execution of
the Write Status Register (WRSR) instruction. The new, updated values take effect at the moment of completion of the
execution of Write Status Register (WRSR) instruction.
Write Status Register (WRSR) Sequence
V_IH
S
V_IL
V_IH
W
V_IL
V_IH
C
V_IL
V_IH
D
V_IL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Status Register In
7 6 5 4 32 1 0
MSB
Q
High-Z
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 13 of 20