R1EX25002ASA00A Datasheet, PDF (14/22 Pages) Renesas Technology Corp – Serial Peripheral Interface Electrically Erasable and Programmable Read Only Memory

R1EX25002Axx00A/R1EX25004Axx00A
Read from Memory Array (READ):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of
the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an
internal address register, and the byte of data at that address is shifted out, on serial data output (Q). The most
significant address (A8) should be sent as fifth bit in the instruction byte.
If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of
data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued
indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at
any time during the cycle. The addressed first byte can be any byte within any page. The instruction is not accepted,
and is not executed, if a Write cycle is currently in progress.
Read from Memory Array (READ) Sequence
V_IH
S
V_IL
V_IH
W
V_IL
V_IH
C
V_IL
V_IH
D
V_IL
Q
0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
8-Bit Address
A8
A7 A6 A5 A3 A2 A1 A0
High-Z
Data Out 1
Data Out 2
7 6 5 4 3 21 07
Note: 1. Depending on the memory size, as shown in the following table, the most significant address bits are don’t
care.
Address Range Bits
Device
Address bits
A8 to A0
Note: 1. A8 is don’t care on the R1EX25002A.
R1EX25004A
R1EX25002A
A7 to A0
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
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