R1EX25002ASA00A Datasheet, PDF (15/22 Pages) Renesas Technology Corp – Serial Peripheral Interface Electrically Erasable and Programmable Read Only Memory

R1EX25002Axx00A/R1EX25004Axx00A
Write to Memory Array (WRITE):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of
the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D).
The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. In the case of the
following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is
being used to write a single byte. The self-timed Write cycle starts, and continues for a period t_WC (as specified in AC
Characteristics). At the end of the cycle, the Write In Progress (WIP) bit is reset to 0.
If, though, chip select (S) continues to be driven low, as shown in the following figure, the next byte of the input data is
shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be
written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the
number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the
beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these
device is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
 If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
 If a Write cycle is already in progress
 If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
 If Write Protect (W) is low
Byte Write (WRITE) Sequence (1 Byte)
V_IH
S
V_IL
V_IH
W
V_IL
V_IH
C
V_IL
V_IH
D
V_IL
0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
A8
8-Bit Address
Data Byte 1
A7 A6 A5 A3 A2 A1 A0 7 6 5 4 3 2 1 0
Q
High-Z
Note: 1. Depending on the memory size, as shown in Address Range Bits table, the most significant address bit is
don’t care.
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 15 of 20