HN58V65A Datasheet, PDF (9/28 Pages) Hitachi Semiconductor – 64 k EEPROM (8-kword x 8-bit) Ready/Busy function, RES function (HN58V66A)

HN58V65A Series, HN58V66A Series
Write Cycle 1 (2.7 V ≤ V_CC < 4.5 V)
Parameter
Symbol Min*³ Typ Max Unit Test conditions
Address setup time
t_AS
0


ns
Address hold time
t_AH
50


ns
CE to write setup time (WE controlled)
t_CS
0


ns
CE hold time (WE controlled)
t_CH
0


ns
WE to write setup time (CE controlled)
t_WS
0


ns
WE hold time (CE controlled)
t_WH
0


ns
OE to write setup time
t_OES
0


ns
OE hold time
t_OEH
0


ns
Data setup time
t_DS
50


ns
Data hold time
t_DH
0


ns
WE pulse width (WE controlled)
t_WP
200 

ns
CE pulse width (CE controlled)
t_CW
200 

ns
Data latch time
t_DL
100 

ns
Byte load cycle
t_BLC
0.3 
30
µs
Byte load window
Write cycle time
t_BL
100 

µs
t_WC
—

10*⁴ ms
Time to device busy
Write start time
Reset protect time*²
Reset high time*^{2, 6}
t_DB
120 

ns
t_DW
0*⁵


ns
t_RP
100 

µs
t_RES
1


µs
Notes: 1. t_DF and t_DFR are defined as the time at which the outputs achieve the open circuit conditions and
are no longer driven.
2. This function is supported by only the HN58V66A series.
3. Use this device in longer cycle than this value.
4. t_WC must be longer than this value unless polling techniques or RDY/Busy are used. This device
automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t_DW if polling techniques or RDY/Busy are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of
WE.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of
CE.
9. See AC read characteristics.
Rev.3.00, Dec. 04.2003, page 9 of 26