HD74CDCV857A Datasheet, PDF (9/13 Pages) Renesas Technology Corp – 2.5-V Phase-lock Loop Clock Driver

HD74CDCV857A
Differential clock outputs are directly terminated by a 120 Ω resistor. Figure 2 is typical usage conditions
of outputs load.
V _DDQ
Device
under _OUT
test
OUT
V _DDQ
R_T=
120 Ω
C = 14 pF
C = 14 pF
Figure 2 Differential signal using direct termination resistor
CLKIN
CLKIN
FBIN
FBIN
t_SPE
Figure 3 Static phase offset
FBOUT
FBOUT
Yx
Yx
t_sk
Yx
Yx
Yx'
Yx'
t_sk
Figure 4 Output skew
Rev.3.00, Oct.09.2003, page 9 of 12