HD74CDCV857A Datasheet, PDF (3/13 Pages) Renesas Technology Corp – 2.5-V Phase-lock Loop Clock Driver

HD74CDCV857A
Pin Function
Pin name
No.
Type
Description
AGND
17
Ground Analog ground. AGND provides the ground reference for the
analog circuitry.
AV_CC
16
CLK, CLK
13, 14
FBIN, FBIN
35, 36
FBOUT, FBOUT 32, 33
PWRDWN
37
Power
Analog power supply. AV_CC provides the power reference for
the analog circuitry. In addition, AV_CC can be used to bypass
the PLL for test purposes. When AV_CC is strapped to ground,
PLL is bypassed and CLK is buffered directly to the device
outputs. This bypass mode is used for RENESAS test.
I
Differential
input
Clock input. CLK provides the clock signal to be distributed by
the HD74CDCV857A clock driver. CLK is used to provide the
reference signal to the integrated PLL that generates the clock
output signals. CLK must have a fixed frequency and fixed
phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization
time is required for the PLL to phase lock the feedback signal to
its reference signal.
I
Differential
input
Feedback input. FBIN provides the feedback signal to the
internal PLL. FBIN must be hard-wired to FBOUT to complete
the PLL. The integrated PLL synchronizes CLK and FBIN so
that there is nominally zero phase error between CLK and
FBIN.
O
Differential
output
I
Feedback output. FBOUT is dedicated for external feedback. It
switches at the same frequency as CLK. When externally wired
to FBIN, FBOUT completes the feedback loop of the PLL.
Output bank enable. PWRDWN is the output enable for all
outputs. When PWRDWN is low, VCO will stop and all outputs
are disabled to a high impedance state. When PWRDWN will
be returned high, PLL will re-synchroniz to CLK frequency and
all outputs are enabled.
GND
1, 7, 8, 18, Ground
24, 25, 31,
41, 42, 48
Ground
V_DDQ
4, 11, 12, Power
15, 21, 28,
34, 38, 45
Power supply
Y
3, 5, 10, 20, O
Clock outputs. These outputs provide low-skew copies of CLK.
22, 27, 29, Differential
39, 44, 46 output
Y
2, 6, 9, 19, O
Clock outputs. These outputs provide low-skew copies of CLK.
23, 26, 30, Differential
40, 43, 47 output
Rev.3.00, Oct.09.2003, page 3 of 12