HD74CDCV857A Datasheet, PDF (8/13 Pages) Renesas Technology Corp – 2.5-V Phase-lock Loop Clock Driver

HD74CDCV857A
Switching Characteristics
Item
Symbol Min Typ Max Unit Test Conditions Notes
Period jitter
t_PER
–75 —
75
ps
See figure 6, 9 7, 8
Half period jitter
t_HPER
–100 —
100 ps
See figure 7, 9 8, 10
Cycle to cycle jitter
t_CC
–75 —
75
ps
See figure 5, 9 10
Static phase offset
t_SPE
–50 —
50
ps
See figure 3, 9 4, 5, 9, 10
Output clock skew
t_sk
—
—
100 ps
See figure 4, 9
Operating clock frequency f_CLK(O) 60
—
200 MHz See figure 9
1, 2
Application clock
frequency
f_CLK(A)
80
167
170
MHz See figure 9
1, 3
Input clock duty cycle
t_DC
40
—
60
%
10
Output clock Slew rate t_SL(O)
1.0
—
2.0
V/ns See figure 9
20% – 80%
PLL stabilization time
t_STAB
—
—
0.1
ms
See figure 9
6, 10
SSC modulation
30
—
50
KHz
10
frequency
SSC clock input
0.00 —
–0.50 %
10
frequency deviation
PLL loop bandwidth
—
3
—
MHz
10
Notes: 1. The PLL must be able to handle spread spectrum induced skew (the specification for this
frequency modulation can be found in the latest Intel PC100 Registered DIMM specification)
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in
which it is not required to meet the other timing parameters.
3. Application clock frequency indicates a range over which the PLL must meet all timing
parameters.
4 Assumes equal wire length and loading on the clock output and feedback path.
5. Static phase offset does not include jitter.
6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its
feedback signal to its reference signal after power up.
7. Period jitter defines the largest variation in clock period, around a nominal clock period.
8. Period jitter and half–period jitter are independent from each other.
9. Conditions at V_DDQ = 2.5 V, Ta = 25°C.
10. Guaranteed by design, not 100% tested in production.
Rev.3.00, Oct.09.2003, page 8 of 12