HD74CDCV857A Datasheet, PDF (6/13 Pages) Renesas Technology Corp – 2.5-V Phase-lock Loop Clock Driver

HD74CDCV857A
Recommended Operating Conditions
Item
Symbol Min
Typ
Max
Unit Conditions Notes
Output supply voltage
Supply voltage
DC input signal voltage
High level input voltage
Low level input voltage
V_DDQ
AV_CC
V_IN
V_IHG
V_ILG
2.3
V_DDQ–0.12
–0.3
1.7
2.5
V_DDQ
—
—
–0.3
—
2.7
V
2.7
V
V_DDQ+0.3 V All pins
1
V_DDQ+0.3 V PWRDWN
input pin
0.7
V PWRDWN
input pin
Input differential voltage V_ID
0.36
—
V_DDQ+0.6 V
3
Output differential voltage V_OD
0.70
—
V_DDQ+0.6 V
Input differential-pair
V_IX
V_DDQ/2 –0.2 —
V_DDQ/2 +0.2 V
2, 3
cross voltage
Output differential-pair
V_OX
V_DDQ/2 –0.15 —
V_DDQ/2 +0.15 V
2, 3
cross voltage
Output current
I_OH
—
—
–12
mA
I_OL
—
—
12
mA
Input clock slew rate
t_SL(I)
1
—
4
V/ns 20% – 80% 3
Operating temperature
T_a
0
—
70
°C
3
Notes:
Inputs pins must be prevent from floating.
Feedback inputs (FBIN, FBIN) may float when the device is in low power mode.
1. DC input signal voltage specifies the allowable dc execution of differential input.
2. Differential cross point voltage is expected to track variations of V_DDQ and is the voltage at which
the differential signals must be crossing. (See figure1)
3. Guaranteed by design, not 100% tested in production.
CLK
V_ID
CLK
Crossing point
Figure 1 Differential input levels
Rev.3.00, Oct.09.2003, page 6 of 12