HD74CDCV857A Datasheet, PDF (11/13 Pages) Renesas Technology Corp – 2.5-V Phase-lock Loop Clock Driver

HD74CDCV857A
Yx, FBOUT
Yx, FBOUT
t _{half cycle n}
t _{half cycle n+1}
t _HCC = t _{half cycle n} - t _{half cycle n+1}
Figure 8 Half cycle to cycle jitter
V _DDQ
AV_CC
Device
under _OUT
test
OUT
AGND
GND
V_DDQ /2
AV_CC/2
Z = 60 Ω
Z = 60 Ω
-V_DDQ /2
C=
14 pF
-V_DDQ /2
C=
14 pF
-V_DDQ /2
R_T=
10 Ω
R_T=
10 Ω
Z = 50 Ω
Z = 50 Ω
V _DDQ
AV_CC
Device
under _OUT
test
V_DDQ
AV_CC
Z = 60 Ω
OUT
AGND
GND
Z = 60 Ω
R_T=
120
C=
14 pF
C=
14 pF
Figure 9 Output load test circuit
Oscillo
scope
R_T=
50 Ω
R_T=
50 Ω
Rev.3.00, Oct.09.2003, page 11 of 12