H8S2472 Datasheet, PDF (873/1250 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.3.2 Transmission
When the transmit function is enabled and the transmit request bit (TR) is set in the E-DMAC
transmit request register (EDTRR), the E-DMAC reads the descriptor used last time from the
transmit descriptor list (in the initial state, the descriptor indicated by the transmission descriptor
start address register (TDLAR)). If the setting of the TACT bit in the read descriptor is active, the
E-DMAC reads transmit frame data sequentially from the transmit buffer start address specified
by TD2, and transfers it to the EtherC. The EtherC creates a transmit frame and starts transmission
to the MII. After DMA transfer of data equivalent to the buffer length specified in the descriptor,
the following processing is carried out according to the TFP value.
1. TFP = 00 or 01 (frame continuation):
Descriptor write-back is performed after DMA transfer.
2. TFP = 01 or 11 (frame end):
Descriptor write-back is performed after completion of frame transmission.
The E-DMAC continues reading descriptors and transmitting frames as long as the setting of the
TACT bit in the read descriptors is "active." When a descriptor with an "inactive" TACT bit is
read, the E-DMAC resets the transmit request bit (TR) in the transmit register and ends transmit
processing (EDTRR).
Rev. 2.00 Aug. 20, 2008 Page 825 of 1198
REJ09B0403-0200