H8S2472 Datasheet, PDF (652/1250 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series

Section 18 I²C Bus Interface (IIC)
Bit
1
Note:
Initial
Bit Name Value R/W Description
IRIC
0
R/(W)*¹ At the end of data transfer in clock synchronous serial
format (rise of the 8th transmit/receive clock)
When a start condition is detected with serial format
selected
When a condition occurs in which the ICDRE or ICDRF
flag is set to 1.
• When a start condition is detected in transmit mode
(when a start condition is detected and the ICDRE flag
is set to 1)
• When transmitting the data in the ICDR register buffer
(when data is transferred from ICDRT to ICDRS in
transmit mode and the ICDRE flag is set to 1, or data
is transferred from ICDRS to ICDRR in receive mode
and the ICDRF flag is set to 1.)
[Clearing conditions]
• When 0 is written in IRIC after reading IRIC = 1
• When ICDR is accessed by DTC * (This may not be a
clearing condition. For details, see the description of
the DTC operation on the next page.
* Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 604 of 1198
REJ09B0403-0200