SH74582_15 Datasheet, PDF (8/14 Pages) Renesas Technology Corp – RENESAS MCU

SH74582
Appendix B.4
Section 11 Address Space
Appendix B
32-bit virtual address space
via CPU
H’C000 0000
H'C00F FFFF
H’C010 0000
H'C3FF FFFF
H’C400 0000
H'C7FF FFFF
H’C800 0000
H'CBFF FFFF
H’CC00 0000
H'CFFF FFFF
H’D000 0000
P3 area
(512 Mbytes)
H'D3FF FFFF
H’D400 0000
H'D7FF FFFF
H’D800 0000
H'D807 FFFF
H’D808 0000
H'DBFF FFFF
H’DC00 0000
H'DFFF FFFF
Area 0
Area 1
29-bit physical address space
Single chip
Internal ROM
(1 Mbyte)
Reserved
Area 2
Area 3
Reserved
Area 4
Area 5
Area 6
Area 7
SHwyRAM
(512Kbytes)
Reserved
Reserved
Note:
The CPU, DMAC, AUDR, and other modules cannot access a reserved area.
But the CPU can access area 7 as a control register area using the MMU.
Figure 11.5 Address Space (P3 Area)
R01DS0240EJ0111 Rev.1.11
Feb 18, 2015
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